1. Technical Field
The present invention relates to semiconductor memory devices and, more particularly, to memory devices and methods of operation thereof.
2. Description of Related Art
There is an increasing demand for semiconductor memory devices capable of random access, high integration and large capacity. Such semiconductor memory devices include flash memory devices, which are used, for example, in portable electronic devices. Semiconductor memory devices which substitute non-volatile material for capacitors in DRAM-like structures have also been introduced. Such devices include, for example, ferroelectric RAM (RFAM) devices that use ferroelectric capacitors, magnetic RAM (MRAM) devices that use a tunneling magneto-resistive (TMR) layer, and phase-change memory devices that use chalcogenide alloys. In particular, phase-change memory devices can be non-volatile and may be fabricated using relatively simple processes. For this reason, it is possible to realize a large capacity memory with a low cost.
A typical conventional phase change memory cell uses a material that may be electrically transitioned between different structured states having different electrical reading characteristics. For example, there are well known memory devices which are formed of chalcogenide material (hereinafter “GST material”) that includes a compound of germanium, antimony and tellurium (GST). The GST material may be transitioned between an amorphous phase showing a relatively high resistivity and a crystalline phase showing a relatively low resistivity. Such a phase change memory cell may be programmed by annealing the GST material. Annealing temperature and duration may determine whether the GST material is left in an amorphous phase or a crystalline phase. A high resistivity state and a low resistivity state may represent programmed values ‘1’ and ‘0’, respectively, and may be detected by measuring the resistivity of the GST material.
In a typical phase change memory device, a memory cell comprises a resistive element and a switching element. FIG. 1 and FIG. 2 each illustrate memory cells of a phase change memory device. Referring to FIG. 1, a memory cell 10 of the phase change memory device includes a variable resistor 11, which is a resistive element, and an access transistor 12, which is a switching element. The variable resistor 11 is connected to a bit line BL. The access transistor 12 is connected between the variable resistor 11 and a ground. A word line WL is connected to a gate of the access transistor 12. The access transistor 12 is turned on when a predetermined voltage is supplied to the word line WL. When the access transistor 12 is turned on, the variable resistor 11 is supplied with a current Ic via the bit line BL.
FIG. 2 is another form of a memory cell 20 of a conventional phase change memory device. The memory cell 20 includes a variable resistor 21 and a diode 22 (a switching element). The diode 22 is turned on or turned off according to a voltage of the word line WL.
FIG. 3 is a diagram illustrating a write current for storing data in the above phase change memory device. Referring to FIG. 3, a pulse 30 of a reset current I_RST for writing reset data, and a pulse 40 of a set current I_SET for writing set data are illustrated.
A phase of the GST material (phase change material) of a memory cell may change according to an amplitude, duration or fall time of a current pulse supplied thereto. The phase of the phase change material corresponding to a set or a reset state may be determined by a volume of the amorphous phase material. Commonly, the amorphous phase corresponds to the reset state, and the crystalline phase corresponds to the set state. The volume of the amorphous phase material may decrease as the amorphous phase proceeds to the crystalline phase. The GST material typically has a resistance that varies according to the volume of the amorphous phase material formed. In other words, data to be written is determined according to the volume of amorphous phase of the GST material formed by different current pulses. A reset current I_RST may be supplied in order to form the above amorphous phase. A set current I_SET may be supplied in order to form the crystalline phase. Typically, a level of the reset current I_RST is greater than a level of the set current I_SET. However, a pulse width ΔT1 of the reset current I_RST is typically relatively less than a pulse width ΔT2 of the set current I_SET. The characteristic of the GST material determined by the write current supplied repeatedly changes according to a lapse.
One of issues that may be raised when realizing a phase change memory device is the endurance of the device. Endurance is the capability of maintaining normal function after repeated data writing and/or reading operations. The ability of endure a large number or writing and/or reading cycles is generally desired in order to support many applications, for example, random access memory applications, solid state disk/drive (SSD) applications and storage applications for mobile devices.